1. Field of the Invention
The present invention relates to a method of erasing information (data) stored in nonvolatile semiconductor memory devices, more particularly, nonvolatile semiconductor memory devices such as EEPROM including a floating gate.
2. Description of the Related Art
A nonvolatile semiconductor memory device is a semiconductor memory in which written data is not lost even when a power source is turned off. This memory has been heretofore diversely researched and developed. Since EPROM (Electrically Programmable Read Only Memory) and a flash memory have a memory cell structure advantageous for a fine formation, they are suitable for high integration of a device. More specifically, since a flash memory can electrically write and erase data, it is receiving attention as a means of replacement of magnetic media, etc. For writing the data onto this flash memory, a channel hot electron method or F-N (Fowler-Nordheim) tunneling is used so as to inject electrons in a floating gate. On the other hand, a known method of erasing the data is drawing out of electrons out from the floating gate by F-N tunnel phenomenon occurring between a source and the floating gate.
Such data erasing methods include a so-called source high voltage erasing method. In this method, a high voltage (for example, 12 V) is applied to a cell source constituting a cell and having MOS structure and then a cell gate (control gate) is grounded, whereby a high electric field is generated between the source and the floating gate, so that the F-N tunnel tunneling is produced. For this method, it is necessary to form a source-side diffusion layer having a high voltage-resistant structure. Thus, this method has a problem, i.e., a difficulty in finely forming the cell.
An erasing method has therefore been proposed in which a source potential is reduced. FIG. 1 shows a technique disclosed in U.S. Pat. No. 5,077,691. In this drawing, the memory cell has the structure described below. An N-type impurity diffusion layer, namely, source 2 and drain 3 are formed on P-type silicon substrate 1. Floating gate 5 is also formed on P-type silicon substrate 1 between the source and the drain through gate oxide film 4. Control gate (cell gate) 7 is further formed on floating gate 5 through inter-gate oxide film 6. Source diffusion layer 2, drain diffusion layer 3, cell gate 7 and P-type silicon substrate 1 are connected to voltage terminals VS, VD, VG and Vsub, respectively.
For this flash memory cell, a voltage of about 5 V and a negative voltage of about -10 V are applied to VS and VG, respectively. A high electric field is thus generated between the source and the floating gate. Consequently, erasing is realized by means of the F-N tunnel tunneling. FIG. 2 is a table showing an operating voltage in this case. In this erasing method, compared to the above-described source high voltage erasing method, the high voltage is not applied to a source terminal. Thus, the source-side diffusion layer does not need the high voltage-resistant structure. Therefore, a fine cell is easily formed. It is also said that this method can reduce the generation of holes having high energy due to inter-band tunneling and can improve the reliability of the gate oxide film under the floating gate.
This improved erasing method is effective for the formation of a fine cell, because a source voltage is reduced. However, the electric field is high between the source and the floating gate. Thus, when many electrons are stored in the floating gate (i.e., when the data is written), a silicon band is considerably curved on the surface of the source diffusion layer near a channel and thus an inter-band tunneling current may be increased. As a result, it is difficult to completely prevent the deterioration of quality of the gate oxide film under the floating gate. In this case, the following solution is suggested. That is, for the purpose of reducing the inter-band tunneling current, the source diffusion layer is constituted of a graded junction in order to relax the electric field between the source-side diffusion layer and the substrate. However, in this solution, the area of the source diffusion layer is increased. Thus, this solution has the difficulty in achieving an original object, namely, in forming a fine cell.